1. Field of the Invention
The present invention relates to a high-level synthesis apparatus for automatically generating a logic circuit for a semiconductor integrated circuit (LSI) represented by a behavioral description (design data) in which processing behaviors of the logic circuit are described. The present invention also relates to a high-level synthesis method using the high-level synthesis apparatus, a method for producing a logic circuit using the high-level synthesis method, and a computer-readable recording medium storing a control program for carrying the high-level synthesis method.
2. Description of the Related Art
Recent micro processing technologies have allowed larger system LSIs. A development environment in which such system LSIs can be efficiently designed and tested is much sought after.
In the 1990s, a logic synthesis tool was developed into practical use. Following this, a behavioral synthesis tool for synthesizing a description having a register transfer level (hereinafter referred to as an RT level) based on a behavioral description in which only behaviors are described excluding information on hardware structure was put into use. The behavioral synthesis tool generated LSI designs, comparable to those manually produced, in a shorter period of time.
When such a behavioral synthesis tool is used, a designer can concentrate his or her efforts on designing an algorithm, which determines an essential behavior of an LSI. Such design of an algorithm largely relies on manual work. As a result, the quality of a circuit can be improved.
At an early stage of the designing of a large digital LSI, such as a system LSI, an algorithm of an entire system is first studied and tested (this process is referred to as an xe2x80x9calgorithm designxe2x80x9d). Here, a software description language, such as a programming language (e.g., the xe2x80x9cC languagexe2x80x9d), is used to design and test an algorithm on a workstation or a personal computer.
Subsequently, individual processes required in a system are described with a hardware description language into behavioral descriptions which will be tested. Therefore, an algorithm previously described with a software description language is described again with a hardware description language into a behavioral description.
Hence, conventionally, a method (high-level synthesis method) for synthesizing a circuit based on an algorithm of an entire system or a behavioral description using the C language was proposed. Such a conventional technique is, for example, disclosed in Japanese Laid-Open Publication No. 10-116302, entitled xe2x80x9cMethod for Designing Integrated Circuit and Integrated Circuit Designed by the Methodxe2x80x9d.
At present, a language having a high level of abstractness, such as the xe2x80x9cC languagexe2x80x9d, is used to describe a behavior of hardware which realizes an application, such as audio or video processing, and to synthesize a hardware circuit (high-level synthesis).
Firstly, a behavioral description language will be described. Hereinafter, the C language is extended for the purpose of behavioral description in the following description. Specifically, the extended C language includes par sentences for explicitly describing parallel operations, commands for data communication between the parallel operations, and communication channels.
An example of such a language is a Bach C language disclosed in xe2x80x9cBach: Environment for LSI Design with C Languagexe2x80x9d, The 11th Workshop on Circuits and Systems in Karuizawa, Apr. 20-21, 1998, and xe2x80x9cHardware Complier Bachxe2x80x9d, TECHNICAL REPORT OF IEICE CRSY97-87 (1997-10). FIG. 15 shows an example of the C language for hardware description. In this example, the following behavior is described.
As shown in FIG. 15, the third line of the behavioral description is the declaration of an int type synchronous communication channel ch.
xe2x80x9cParxe2x80x9d on the sixth line is of a par sentence, which explicitly indicates parallel operations. Here, the sentence indicates that two blocks therein are operated in parallel.
The seventh line describes a first thread operation, indicating that a data communication command xe2x80x9csendxe2x80x9d is used to send a value 10 to the communication channel ch.
The eighth line describes the next thread operation, indicating that a data communication command xe2x80x9creceivexe2x80x9d is used to receive data from the communication channel ch, and substitute the received data into a variable x.
The tenth line indicates that after the par sentence on lines 6-9 is executed, the content of the variable x is output as an integer type decimal number to xe2x80x9cstdoutxe2x80x9d.
Next, the processes of high-level synthesis will be explained based on an exemplary high-level synthesis as proposed by Japanese Laid-Open Publication No. 10-116302, entitled xe2x80x9cMethod for Designing Integrated Circuit and Integrated Circuit Designed by the Methodxe2x80x9d. The flow of high-level synthesis is roughly divided into four stages: (N1) to (N4). The explanation will be carried out with reference to the function blocks in FIG. 16.
(N1) A behavioral description which describes an algorithm of the processing behavior of a circuit is analyzed.
(N2) The processing behavior is divided into threads which are asynchronously operated in parallel.
(N3) For each thread, the following processes (N3a) to (N3f) are carried out.
(N3a) Synthesis of CDFG
CDFG (control data flow graph) is a graph representing dependence relationships between computations in terms of execution order. In a CDFG, computations, inputs and outputs are represented by nodes, and data dependence relationships are represented by directed branches.
(N3b) Scheduling
A time corresponding to a clock, called a step, is allocated successively to each of the computations, the inputs and the outputs in the CDFG.
(N3c) Allocation
Computation units, registers, and input and output pins required for execution of the scheduled CDFG are generated. The computation units are allocated to the computations in the CDFG. The registers are allocated to data dependence branches across clock borders. The input and output pins are allocated to the input and the outputs.
(N3d) Generation of Data Path
Data paths corresponding to the respective data dependence relationship branches in the CDFG are generated.
(N3e) Generation of Controller
A controller for controlling the computation units, registers and multiplexers generated during the allocation and the generation of the data paths is generated.
(N3f) Generation of RT Level Circuit
A circuit description of the circuit generated by the above-described processes is generated using a hardware description language, such as VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language], and the like.
(N4) RT level circuits each for the respective threads (partial circuit) are integrated together into a single RT level circuit.
Next, the parallel operation and the communication in the high-level synthesis will be explained.
Hereinafter, it is assumed that in communication using synchronous channels (hereinafter referred to as synchronous channel communication), data is transferred after both a sender-end thread (hereinafter referred to as a send-thread) and a receiver-end thread (hereinafter referred to as a receive-thread) are in a state of readiness for communication.
As one method for realizing synchronous channel communication, a circuit configuration as shown in FIG. 17, which employs a handshake control signal, may be used. In such a circuit configuration, a send-thread circuit has the following ports. An (I) in the name of each port of the circuit indicates that the port is an input port, while an (O) indicates that the port is an output port. xe2x80x9cwtxxe2x80x9d represents a control line port for a send request signal (or a send completion signal) to a receiver end. xe2x80x9cwrxxe2x80x9d represents a control line port for a receive request signal (or a receive completion signal) from a receiver end. xe2x80x9cwdataxe2x80x9d represents a data line port at a sender end.
On the other hand, a receive-thread circuit has the following ports. An (I) in the name of each port of the circuit indicates that the port is an input port, while an (O) indicates that the port is an output port. xe2x80x9crrxxe2x80x9d represents a control line port for a receive request signal (or a receive completion signal) to a receiver end. xe2x80x9crtxxe2x80x9d represents a control line port for a send request signal (or a send completion signal) from a receiver end. xe2x80x9crdataxe2x80x9d represents a data line port at a receiver end.
FIG. 18 shows an exemplary timing chart of data transfer in the circuit configuration. It should be noted that the voltage of each control line in the initial state is assumed to be at a xe2x80x9cLOWxe2x80x9d level.
It is assumed that a xe2x80x9csend commandxe2x80x9d is first executed, and thereafter, a xe2x80x9creceive commandxe2x80x9d is executed. As shown in FIG. 18, for example, a send-thread (thread 1) executes a xe2x80x9csend commandxe2x80x9d in a clock cycle c1, and a receive-thread (thread 2) executes a xe2x80x9creceive commandxe2x80x9d in a clock cycle c3.
The send-thread outputs data d1 to the data line port xe2x80x9cwdataxe2x80x9d in the clock cycle c1, and causes the voltage of the control line port xe2x80x9cwtx(O)xe2x80x9d to be at a xe2x80x9cHIGHxe2x80x9d level. Further, the send-thread waits until the voltage of the control line port xe2x80x9cwrx(I)xe2x80x9d goes xe2x80x9cHIGHxe2x80x9d. When the voltage of the control line port xe2x80x9cwrx(I)xe2x80x9d goes xe2x80x9cHIGHxe2x80x9d, the send thread causes the voltage of the control line port xe2x80x9cwtx(O)xe2x80x9d to go xe2x80x9cLOWxe2x80x9d and ends the data output to the data line port xe2x80x9cwdataxe2x80x9d at the next clock cycle (c4).
On the other hand, the receive-thread causes the voltage of the control line port xe2x80x9crrx(O)xe2x80x9d to be at the xe2x80x9cHIGHxe2x80x9d level in the clock cycle c3. Here, since the voltage of the control line port xe2x80x9crtx(I)xe2x80x9d is at the xe2x80x9cHIGHxe2x80x9d level, the receive-thread references the data d1 at the data line port xe2x80x9crdataxe2x80x9d and causes the voltage of the control line port xe2x80x9crrx(O)xe2x80x9d to go xe2x80x9cLOWxe2x80x9d at the next clock cycle c4. Thus, data communication is ended.
Next, it is assumed that a xe2x80x9creceive commandxe2x80x9d is first executed, and thereafter, a xe2x80x9csend commandxe2x80x9d is executed.
As shown in FIG. 18, for example, the receive-thread executes the xe2x80x9creceive commandxe2x80x9d in a clock cycle c7, while the send-thread executes the xe2x80x9csend commandxe2x80x9d in a clock cycle c9.
The receive-thread causes the voltage of the control line port xe2x80x9crrx(O)xe2x80x9d to be at the xe2x80x9cHIGHxe2x80x9d level in the clock cycle c7. Further, the receive-thread waits until the voltage of the control line port xe2x80x9crtx(I)xe2x80x9d goes xe2x80x9cHIGHxe2x80x9d. When the voltage of the control line port xe2x80x9crtx(I)xe2x80x9d goes xe2x80x9cHIGHxe2x80x9d, the receive-thread references data d2 of the data line port xe2x80x9crdataxe2x80x9d and causes the voltage of the control line port xe2x80x9crrx(O)xe2x80x9d to go xe2x80x9cLOWxe2x80x9d in a clock cycle c10.
The send-thread outputs the data d2 to the data line port xe2x80x9cwdataxe2x80x9d and causes the voltage of the control line port xe2x80x9cwtx(O)xe2x80x9d to go xe2x80x9cHIGHxe2x80x9d in the clock cycle c9. Here, since the voltage of the control line port xe2x80x9crrx(O)xe2x80x9d is at the xe2x80x9cHIGHxe2x80x9d level, the send-thread causes the voltage of the control line port xe2x80x9cwtx(O)xe2x80x9d to go xe2x80x9cLOWxe2x80x9d and ends data output to the data line port xe2x80x9cwdataxe2x80x9d at the next clock cycle c10. Thus, data communication is ended.
In this manner, after the send-thread causes the voltage of the control line port xe2x80x9cwtx(O)xe2x80x9d to go xe2x80x9cHIGHxe2x80x9d, when the voltage of the control line port xe2x80x9cwrx(I)xe2x80x9d goes xe2x80x9cHIGHxe2x80x9d, the xe2x80x9csend commandxe2x80x9d is ended. After the receive-thread causes the voltage of the control line port xe2x80x9crrx(O)xe2x80x9d to go xe2x80x9cHIGHxe2x80x9d, when the voltage of the control line port xe2x80x9crtx(I)xe2x80x9d goes xe2x80x9cHIGHxe2x80x9d, the xe2x80x9creceive commandxe2x80x9d is ended. When these xe2x80x9csend commandxe2x80x9d and xe2x80x9creceive commandxe2x80x9d are executed in the same clock cycle Cn, data communication is ended in a clock cycle Cn+1.
In the field of consumer-oriented portable devices or communication devices, there has been a demand for elongation of the life of a battery, improvement of the reliability of LSI, a reduction in heat generation, cost reduction in cooling and packaging of LSI, and the like. To meet the demands, the power consumption of a circuit has to be lowered.
Generally, the power consumption P of a CMOS logic circuit is represented as:
P=xcex1xc2x7Cxc2x7V2xc2x7f
where xcex1 indicates the switching rate of the circuit, C indicates the load capacitance thereof, V indicates the operating voltage thereof, and f indicates the operating frequency thereof.
According to the expression, a decrease in the switching rate can lead to a reduction in the power consumption.
Generally, a synthesized RT level circuit is composed of a plurality of partial circuits corresponding to threads which are asynchronously operated in parallel, and is always driven by a clock.
On the other hand, when synchronous channel communication is carried out between threads, even if one of a send-thread or a receive-thread starts data communication, one of the methods may wait until the other is ready. For example, in the clock cycles c2 and c3 shown in FIG. 18 the send-thread is in a wait state, while in the clock cycles c8 and c9 the receive-thread is in a wait state. When the thread is in a wait state, even if the corresponding partial circuit is not operated, the output of the circuit is not affected.
However, in the above-described conventional configuration, even when a certain thread is in a wait state, a clock is always supplied. As a result, although the output of the circuit is not affected, power is uselessly consumed by the supply of a clock in a partial circuit.
According to one aspect of the present invention, a high-level synthesis apparatus for synthesizing a register transfer level logic circuit from a behavioral description describing a processing operation of the circuit, comprises a low power consumption circuit generation section for generating a low power consumption circuit which stops or inhibits circuit operations of partial circuits constituting the logic circuit only when the partial circuits are in a wait state, so to achieve low power consumption. The low power consumption circuit generation section is synthesized along with the logic circuit.
In one embodiment of this invention, the low power consumption circuit generation section generates the low power consumption circuit which stops or reduces clock supply to the partial circuits when the partial circuits are in a wait state, based on synchronous processing information extracted from behavioral description information including synchronous communication information.
According to another aspect of the present invention, a high-level synthesis method is provided for synthesizing a register transfer level logic circuit from a behavioral description describing a processing operation of the logic circuit so as to construct a desired logic circuit, and producing the synthesized logic circuit. The method comprises the step of synthesizing, along with the logic circuit, a low power consumption circuit which stops or inhibits circuit operations of partial circuits constituting the logic circuit only when the partial circuits are in a wait state, so to achieve low power consumption.
In one embodiment of this invention, the synthesized low power consumption circuit stops or reduces the operations of partial circuits by stopping or reducing clock supply to the partial circuits.
In one embodiment of this invention, the synthesized low power consumption circuit controls the clock supply using a signal indicating the wait state.
In one embodiment of this invention, the synthesized low power consumption circuit stops or inhibits the operations of the partial circuits when a data sender-end circuit or a data receiver-end circuit is in a wait state during data transfer between the partial circuits.
In one embodiment of this invention, the synthesized low power consumption circuit generates a signal indicating the wait state of the partial circuits using a control signal for synchronous communication, and drives the partial circuits using a gated clock generated using the signal indicating the wait state of the partial circuits, so as to achieve low power consumption.
In one embodiment of the synthesizing step is carried out based on synchronous processing information extracted from behavioral description information including synchronous communication information, and the synthesized low power consumption circuit stops or reduces the operations of partial circuits by stopping or reducing clock supply to the partial circuits.
In one embodiment of this invention, the high-level synthesis method further comprises the steps of generating a signal for each partial circuit indicating that the partial circuit is in a wait state based on synchronous processing information extracted from behavioral description information including the synchronous communication information, and generating a gated clock for each partial circuit using the signal. The synthesized low power consumption circuit drives the partial circuit using the generated gated clock, and stops the output of the gated clock supplied to the partial circuit when the partial circuit is in a wait state.
According to another aspect of the present invention, a method is provided for producing a logic circuit, in which the above-described high-level synthesis method is used to design the logic circuit.
According to another aspect of the present invention, a computer readable recording medium comprises a control program for executing the above-described high-level synthesis method.
Thus, the invention described herein makes possible the advantages of providing a high-level synthesis apparatus capable of generating a low power consumption circuit configuration in which wasted power consumption when a thread is in a wait state can be reduced, a high-level synthesis method using the high-level synthesis apparatus, a method for producing a logic circuit using the high-level synthesis method, and a computer readable recording medium recording a control program for executing the high-level synthesis method.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.